PC [Project] Build a Computer in Terraria!

Your RAM could easily be reduced from 6x3 to 2x3 blocks per bit if you use a purely faulty gate based design like this:

YWrHDbl.png


Basically, when the red wire is triggered, the value stored in the gate is swapped with the value being carried by the blue wire. What you could do then, is a have a bus of 16 blue/green alternating wires to represent the currently accessed register. The bits in the bus can be modified to alter the value of that register. When the input address changes, the value in the bus would be swapped with the currently empty value in the register and then swapped again with the value of the register at the new input address.
If you alternate between blue and green wires, you can tile this gate easily in a 2x3 block space per bit, making it 3 times as compact as your current design.
If you want, I can send you the world file for my last RAM design so you can take a look at it.
 
Your RAM could easily be reduced from 6x3 to 2x3 blocks per bit if you use a purely faulty gate based design like this:

YWrHDbl.png


Basically, when the red wire is triggered, the value stored in the gate is swapped with the value being carried by the blue wire. What you could do then, is a have a bus of 16 blue/green alternating wires to represent the currently accessed register. The bits in the bus can be modified to alter the value of that register. When the input address changes, the value in the bus would be swapped with the currently empty value in the register and then swapped again with the value of the register at the new input address.
If you alternate between blue and green wires, you can tile this gate easily in a 2x3 block space per bit, making it 3 times as compact as your current design.
If you want, I can send you the world file for my last RAM design so you can take a look at it.
Ah, I got it. What a brilliant design! I can imagine how it works, and actually, I have an idea to reduce it to 1.5*3 blocks per bit. I'd like to have your world file to see if our thoughts meet.
Capture 2018-11-26 15_41_11.png

BTW, my previous design is actually 1.5*6 blocks per bit, instead of 3*6.
So, maybe I'll use the 1.5*3 design. Thank you very much!
 
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There is no refreshing rate for wiring. Every time a physical power source (power sources except logic gates) activates, it triggers a so-called refreshing of wiring (reference). Since there is no limit on the number of activating physical power sources in a tick (reference), there is no limit on refreshing rate of wiring.
Well, then, whats the limit on a clock circuit?
 
Well, then, whats the limit on a clock circuit?
Simple answer: there is no limit by the game code.
Full answer: By stacking dummy engines, it's easy to build a 100/tick engine, or 6000Hz if there is no lag. Another engine can achieve far beyond this (easily over 10k/tick) but requires the player to stay in it. However, when an engine is fast enough, the lag limits the Hertz. Since the lag is caused by operations, the limit of Hertz is decided by the speed of the real computer. Actually, through my unposted test, switching 40k gemspark blocks per tick on my computer increases the period of a 5 second timer to 30 seconds. This means that the frequency that I can switch gemspark blocks is capped by around (40k/tick)*300tick/30sec=400kHz. While by putting over 400k gemspark blocks, it's easy to achieve an in-game frequency over 400k/tick. (I didn't say it's an engine. I'm just showing the difference between in-game frequency and Hertz.) Overall, in-game frequency is unlimited, but Hertz is limited.
 
Simple answer: there is no limit by the game code.
Full answer: By stacking dummy engines, it's easy to build a 100/tick engine, or 6000Hz if there is no lag. Another engine can achieve far beyond this (easily over 10k/tick) but requires the player to stay in it. However, when an engine is fast enough, the lag limits the Hertz. Since the lag is caused by operations, the limit of Hertz is decided by the speed of the real computer. Actually, through my unposted test, switching 40k gemspark blocks per tick on my computer increases the period of a 5 second timer to 30 seconds. This means that the frequency that I can switch gemspark blocks is capped by around (40k/tick)*300tick/30sec=400kHz. While by putting over 400k gemspark blocks, it's easy to achieve an in-game frequency over 400k/tick. (I didn't say it's an engine. I'm just showing the difference between in-game frequency and Hertz.) Overall, in-game frequency is unlimited, but Hertz is limited.
And here i was thinking the limit was 60hz...
God, imagine what you could do with this!
 
Ah, I got it. What a brilliant design! I can imagine how it works, and actually, I have an idea to reduce it to 1.5*3 blocks per bit. I'd like to have your world file to see if our thoughts meet.
View attachment 213846
BTW, my previous design is actually 1.5*6 blocks per bit, instead of 3*6.
So, maybe I'll use the 1.5*3 design. Thank you very much!

Here's the world file containing the complete RAM, it's pretty big (64 KB of RAM), so it might take a bit to load:
https://drive.google.com/open?id=19CsZS4fUfFJedQCtQ9Z848nDSGONFC33
[doublepost=1543259054,1543258850][/doublepost]Also, what do you mean by 1.5x6 blocks? Each bit in your design takes up 18 blocks of space.
 
Here's the world file containing the complete RAM, it's pretty big (64 KB of RAM), so it might take a bit to load:
OMG. I've never thought of 64KB. The multiplexer alone would cause terrible lag. I had a glimpse of it, but I'm so bad at reading junction boxes. I thought its outer workings are nearly the same as the previous design's, although their inner workings are different.
Also, what do you mean by 1.5x6 blocks? Each bit in your design takes up 18 blocks of space.
The 3*6 blocks are shared by two bits, so one bit takes 1.5*6 space. I'm not sure if you mix up the RAM and the registers, because my registers take 6*3 blocks per bit.
 
The 3*6 blocks are shared by two bits, so one bit takes 1.5*6 space. I'm not sure if you mix up the RAM and the registers, because my registers take 6*3 blocks per bit.

Yeah, I was mixing them up. Why don't you use the RAM's design for the registers as well? What functional advantage do the registers have?
 
Yeah, I was mixing them up. Why don't you use the RAM's design for the registers as well? What functional advantage do the registers have?
Each register can be read and written once per cycle, which means it's convenient to transport data from one register to another or do a binary operation in a cycle. On the other hand, there are few registers, so the multiplexer does not cause lag.
When it comes to numerous lamps and gates in terraria, we have to consider the number of working lamps and gates in a cycle because that number decides the efficiency of the circuit. The lamps' and gates' operations are lined up in the game instead of parallel in reality. So larger memory must be slower because there are more working lamps and gates in the multiplexer.
[doublepost=1543838584,1543315701][/doublepost]Different shifter designs

My favorite which can perform logical/arithmetic left/right shift. The multiplexer decides which digit to start and the bottom green wire decides if it's logical or arithmetic. It has no requirement for the input time of two operands and is easy to activate, while the following two designs have to be controlled carefully to prevent missing pulses.
Capture 2018-12-03 11_41_03.png


Logical right shifter and arithmetic right shifter using combinatoric logic. They divide the shift operation into 3 steps: shift 1 digit, shift 2 digits, and shift 4 digits.
Capture 2018-12-03 11_42_24.png


The simplest shifter. It doesn't cause much less lag despite its tiny size.
Capture 2018-12-03 11_55_04.png

[doublepost=1545744445][/doublepost]RAM Designs
There are 2 known RAM designs created by @Programmatic . They work differently and each has its advantages and disadvantages
The first takes 3*3 per bit for the horizontal type and 1.5*6 per bit for the vertical type. Its writing progress relies on values and requires extra wiring to stabilize.
The second is more compact, taking 2*3 per bit for the horizontal type and 1.5*3 per bit for the vertical type. Gaining control of a new word has to be one step later than returning control of the last word, making this design the hardest to control. Writing progress doesn't rely on values, though. Also, it's the slowest one because activated logic lamps are a lot more than those of the other two designs.
I'm using a combination of these two designs. Since the second design is compact, I use it as the basic structure. As it has a high complexity, I reduce the size to 64B and use 4 chips to achieve a 256B RAM. To switch controls of the 4 chips, I use the first design. From the captures below, you can see that the first design appears on the right. This design is smaller as well as faster than before.
upload_2018-12-25_13-40-53.png
upload_2018-12-25_13-40-33.png
 
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I would like to help, if you're ok w/ that.

I know basic cpu architecture and I would like to learn from this experience.
 
I would like to help, if you're ok w/ that.

I know basic cpu architecture and I would like to learn from this experience.
That's great! This experience does teach me a lot. I rarely update this thread because there are few people following.
I'd like to know how much you know about terraria wiring because it decides how many techniques and tricks you or me have to post before starting the deep discussion of this project. Do you know operation order of logic gates, or how does terraria execute logic circuits? What's the most difficult circuit you have made in terraria?
 
I'd also be willing to collaborate on the project, though I don't have a ton of free time, and I haven't quite fully grasped your designs just yet.
 
I may not understand 80% of this, but the 20% I do understand is mind-blowing. Great job so far!
 
Could I perhaps have access to the vertical wire design? The forum link is broken and it would help my current project immensely.
Thanks in advance, Dolpenguin
 
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